Traffic light signaling and operation binary
These count numbers from counter are decoded by interval decoder which selects the set of lamps at the intersection which are to be energized during the inverval from interval selector The lines on the cable are energized by the backup transmitter 10 at the master controller. The clock generator through the frequency divider supplies the clock pulses to operate the counter traffic light signaling and operation binary a counting cycle. When the first bit in the train arrives at the end 52a of the shift register 52, the arrival is detected by bit de tector 53 which feeds a signal to logic controller For the second task, a digital circuit was designed and built to output the proper signaling sequence for a 4-way intersection.
Timing for the cycle is derived from keys on the rotating dial which actuate the cam shafts stepping mechanism to change the intervals traffic light signaling and operation binary the cycle. For the second task traffic lightswe again connected the inputs to the first four Indicators. Thus, the pedestrian, vehicle, and status data received at the master is identified as to its source without necessitating the accompanying address signals. The vehicle and pedestrian detection signals are then shifted out of the shift register and to a transmitter at the local controller.
As already mentioned, control programs for all intersections are stored in the control computer 1 at the master. During semi-actuated or full actuated operation, the status of each traffic light signaling and operation binary circuit is determined by the pedestrian and vehicle data from the same intersection. The program schedule is unique to each intersection and includes the desired status of each lamp circuit during every part of every cycle. A binary traffic light signaling and operation binary is transmitted if the waveform transition during the window goes in the same direction as the previous transition at the previous clock transition. The output of differentiator 92 which is waveform B is clipped by clipper circuit 97 producing waveform D that is fed along the waveform H to a D flip-flop circuit
The output of the NAND gate is also applied to K input of the JK flip-flop so that the 6 output terminal thereof is at a high potential and the 0 output terminal is at a low potential. The interval between these overflow pulses is related to the cycle length number inserted from the matrices. At each local controller such as traffic light signaling and operation binary controller A is a receiver 20 and transmitter 21 which receive and relay the data signal trains from the master controller transmitter 8 on to the next controller which in this case is local controller B.
Since we could see the input and the resulting outputs together on the logic indicators, it was easier to test the circuit. Traffic light signaling and operation binary delays are included to insure that the buffer register is cleared before the data from shift register 52 is inserted into it. We didn't have any problems with the other segments. If the received signal train checks alright, the local controller 7 to which it is addressed feeds the data bits from the shift register to a buffer register that controls the lights at the intersection turning lights off or on as dictated by the data bits.
The format of data signal trains transmitted is shown by the waveform type diagrams in FIG. If the local intersection is at the proper offset, then at the time of the stop pulse from the compare circuitthe appropriate offset select line in cable from the master traffic light signaling and operation binary will open briefly causing the offset matrices in to output a signal in lines which causes the stop signal output from comparator to be removed and the 1 percent timer will continue pulsing the counter which traffic light signaling and operation binary continue to count in 1 percent increments of the cycle. The flipflop circuits incorporate therein two binary circuits in each package anc can be implemented by the Texas Instruments SN